1. Field of the Invention
The present invention generally relates to metal oxide semiconductor field effect transistors (MOSFETs) and more particularly to a double-gate MOSFET that has several advantages over conventional single-gate MOSFETs.
2. Description of the Related Art
It is conventionally known that a double-gate MOSFET has several advantages of over conventional single-gate MOSFET structures (dual-gates are side by side, while double-gates form a top and bottom gate structure). For example, the double-gate MOSFET structure has higher transconductance, lower parasitic capacitance and superior short-channel characteristics when compared to single-gate MOSFET structures. Various simulations have shown that a 30 nm channel double-gate MOSFET will show very high transconductance (2300 mS/mm) and very fast switching speeds. Moreover, good short-channel characteristics are obtained down to a 20 nm channel length, which does not require doping. Therefore, double-gate MOSFETs circumvent tunneling breakdown, and avoid the dopant quantization and impurity scattering associated with the conventional doping required in single-channel MOSFET structures.
However there is no conventional method of making a double-gate MOSFET structure which has both the top and bottom gate self-aligned to the source/drain suicides and which produces a planarized surface after the formation of the source/drain and gate structures. Conventional efforts to form a double-gate MOSFET structure generally fall into three categories.
One method etches silicon into a pillar structure and deposits gates around the pillar structure. However, with this method, it is difficult to form thin vertical pillars (e.g., 10 nm) that are free of reactive ion etching (RIE) damage and to maintain good thickness control.
Another method forms a conventional single-gate MOSFET and uses either selective epitaxy or bond-and-etch-back techniques to form the second gate. However, with this method, it is difficult to keep the top and bottom gate oxides at the same thickness and to align the gates with each other.
A third method begins with a thin SOI film, and patterns tunnels under the SOI film. Then, gate electrodes are deposited in the tunnel around the SOI film. However, this method also suffers silicon thickness control problems and gate alignment problems.
Therefore, there is a need for a method and structure of forming a doublegate MOSFET structure which provides a planarized surface after the formation of the source/drain and gate structures and which allows for the gate and source/drain suicides to be self-aligned.